[Avida-SVN] r3448 - in development/source: actions cpu main

[connel42 at myxo.css.msu.edu]

Author: connel42
Date: 2009-10-06 09:52:19 -0400 (Tue, 06 Oct 2009)
New Revision: 3448

Modified:
   development/source/actions/PrintActions.cc
   development/source/cpu/cHardwareCPU.cc
   development/source/cpu/cHardwareCPU.h
   development/source/main/cPopulation.cc
Log:
Fixed some bugs in my print actions, added a few bitstring operators

Modified: development/source/actions/PrintActions.cc
===================================================================
--- development/source/actions/PrintActions.cc	2009-10-05 19:54:41 UTC (rev 3447)
+++ development/source/actions/PrintActions.cc	2009-10-06 13:52:19 UTC (rev 3448)
@@ -3136,6 +3136,7 @@
       }
       
       df.WriteRaw("];");
+      df.Endl();
     }
   };
 

Modified: development/source/cpu/cHardwareCPU.cc
===================================================================
--- development/source/cpu/cHardwareCPU.cc	2009-10-05 19:54:41 UTC (rev 3447)
+++ development/source/cpu/cHardwareCPU.cc	2009-10-06 13:52:19 UTC (rev 3448)
@@ -180,6 +180,7 @@
     tInstLibEntry<tMethod>("inc", &cHardwareCPU::Inst_Inc, nInstFlag::DEFAULT, "Increment ?BX? by one"),
     tInstLibEntry<tMethod>("dec", &cHardwareCPU::Inst_Dec, nInstFlag::DEFAULT, "Decrement ?BX? by one"),
     tInstLibEntry<tMethod>("zero", &cHardwareCPU::Inst_Zero, 0, "Set ?BX? to zero"),
+    tInstLibEntry<tMethod>("all1s", &cHardwareCPU::Inst_All1s, 0, "Set ?BX? to all 1s in bitstring"),
     tInstLibEntry<tMethod>("neg", &cHardwareCPU::Inst_Neg),
     tInstLibEntry<tMethod>("square", &cHardwareCPU::Inst_Square),
     tInstLibEntry<tMethod>("sqrt", &cHardwareCPU::Inst_Sqrt),
@@ -191,10 +192,15 @@
     tInstLibEntry<tMethod>("div", &cHardwareCPU::Inst_Div, 0, "Divide BX by CX and place the result in ?BX?"),
     tInstLibEntry<tMethod>("mod", &cHardwareCPU::Inst_Mod),
     tInstLibEntry<tMethod>("nand", &cHardwareCPU::Inst_Nand, nInstFlag::DEFAULT, "Nand BX by CX and place the result in ?BX?"),
+    tInstLibEntry<tMethod>("or", &cHardwareCPU::Inst_Or),
     tInstLibEntry<tMethod>("nor", &cHardwareCPU::Inst_Nor),
     tInstLibEntry<tMethod>("and", &cHardwareCPU::Inst_And),
     tInstLibEntry<tMethod>("order", &cHardwareCPU::Inst_Order),
     tInstLibEntry<tMethod>("xor", &cHardwareCPU::Inst_Xor),
+    
+    // Instructions that modify specific bits in the register values
+    tInstLibEntry<tMethod>("setbit", &cHardwareCPU::Inst_Setbit, nInstFlag::DEFAULT, "Set the bit in ?BX? specified by ?BX?'s complement"),
+    tInstLibEntry<tMethod>("clearbit", &cHardwareCPU::Inst_Clearbit, nInstFlag::DEFAULT, "Clear the bit in ?BX? specified by ?BX?'s complement"),
 
 		// treatable instructions
 		tInstLibEntry<tMethod>("nand-treatable", &cHardwareCPU::Inst_NandTreatable, nInstFlag::DEFAULT, "Nand BX by CX and place the result in ?BX?, fails if deme is treatable"),
@@ -2608,6 +2614,18 @@
   return true;
 }
 
+bool cHardwareCPU::Inst_All1s(cAvidaContext& ctx)
+{
+  const int reg_used = FindModifiedRegister(REG_BX);
+  GetRegister(reg_used) = 0;
+  
+  for(int i=0; i< ((int) sizeof(int) * 8); i++) {
+    GetRegister(reg_used) |= 1 << i;
+  }
+    
+  return true;
+}
+
 bool cHardwareCPU::Inst_Neg(cAvidaContext& ctx)
 {
   const int src = FindModifiedRegister(REG_BX);
@@ -2753,6 +2771,15 @@
   return true;
 }
 
+bool cHardwareCPU::Inst_Or(cAvidaContext& ctx)
+{
+  const int dst = FindModifiedRegister(REG_BX);
+  const int op1 = REG_BX;
+  const int op2 = REG_CX;
+  GetRegister(dst) = (GetRegister(op1) | GetRegister(op2));
+  return true;
+}
+
 bool cHardwareCPU::Inst_And(cAvidaContext& ctx)
 {
   const int dst = FindModifiedRegister(REG_BX);
@@ -2789,6 +2816,33 @@
   return true;
 }
 
+// Set the bit in ?BX? specified in its complement register
+bool cHardwareCPU::Inst_Setbit(cAvidaContext& ctx)
+{
+  const int to_set = FindModifiedRegister(REG_BX);
+  const int bit_reg = FindNextRegister(to_set);
+  
+  const int bit_to_set = max(0, GetRegister(bit_reg)) % (sizeof(int) * 8);
+
+  GetRegister(to_set) |= 1 << bit_to_set;
+
+  return true;
+}
+
+// Clear the bit in ?BX? specified in its complement register
+bool cHardwareCPU::Inst_Clearbit(cAvidaContext& ctx)
+{
+  const int to_clear = FindModifiedRegister(REG_BX);
+  const int bit_reg = FindNextRegister(to_clear);
+  
+  const int bit_to_clear = max(0, GetRegister(bit_reg)) % (sizeof(int) * 8);
+    
+  GetRegister(to_clear) &= ~(1 << bit_to_clear);
+  
+  return true;
+}
+
+
 bool cHardwareCPU::Inst_Copy(cAvidaContext& ctx)
 {
   const int op1 = REG_BX;

Modified: development/source/cpu/cHardwareCPU.h
===================================================================
--- development/source/cpu/cHardwareCPU.h	2009-10-05 19:54:41 UTC (rev 3447)
+++ development/source/cpu/cHardwareCPU.h	2009-10-06 13:52:19 UTC (rev 3448)
@@ -433,6 +433,7 @@
   bool Inst_ValPolyC(cAvidaContext& ctx);
   bool Inst_Inc(cAvidaContext& ctx);
   bool Inst_Dec(cAvidaContext& ctx);
+  bool Inst_All1s(cAvidaContext& ctx);
   bool Inst_Zero(cAvidaContext& ctx);
   bool Inst_Not(cAvidaContext& ctx);
   bool Inst_Neg(cAvidaContext& ctx);
@@ -448,10 +449,15 @@
   bool Inst_Div(cAvidaContext& ctx);
   bool Inst_Mod(cAvidaContext& ctx);
   bool Inst_Nand(cAvidaContext& ctx);
+  bool Inst_Or(cAvidaContext& ctx);
   bool Inst_Nor(cAvidaContext& ctx);
   bool Inst_And(cAvidaContext& ctx);
   bool Inst_Order(cAvidaContext& ctx);
   bool Inst_Xor(cAvidaContext& ctx);
+  
+  // Bit-setting instructions
+  bool Inst_Setbit(cAvidaContext& ctx);
+  bool Inst_Clearbit(cAvidaContext& ctx);
 
   // Double Argument Math that are treatable
 	bool Inst_NandTreatable(cAvidaContext& ctx);

Modified: development/source/main/cPopulation.cc
===================================================================
--- development/source/main/cPopulation.cc	2009-10-05 19:54:41 UTC (rev 3447)
+++ development/source/main/cPopulation.cc	2009-10-06 13:52:19 UTC (rev 3448)
@@ -3260,6 +3260,7 @@
   } //End iterating through demes
   
   df.WriteRaw("];");
+  df.Endl();
 }