[Avida-SVN] r3367 - development/source/cpu

[beckma24 at myxo.css.msu.edu]

Author: beckma24
Date: 2009-08-13 21:01:07 -0400 (Thu, 13 Aug 2009)
New Revision: 3367

Modified:
   development/source/cpu/cHardwareBase.h
   development/source/cpu/cHardwareCPU.cc
   development/source/cpu/cHardwareCPU.h
Log:
Added instructions maskoff-lower15bits, maskoff-lower14bits, and maskoff-lower13bits

Modified: development/source/cpu/cHardwareBase.h
===================================================================
--- development/source/cpu/cHardwareBase.h	2009-08-13 21:51:41 UTC (rev 3366)
+++ development/source/cpu/cHardwareBase.h	2009-08-14 01:01:07 UTC (rev 3367)
@@ -81,6 +81,9 @@
 	static const unsigned int MASK24       = 0xFFFFFF;
 
 	static const unsigned int MASKOFF_LOWEST16       = 0xFFFF0000;
+	static const unsigned int MASKOFF_LOWEST15       = 0xFFFF8000;
+	static const unsigned int MASKOFF_LOWEST14       = 0xFFFFC000;
+	static const unsigned int MASKOFF_LOWEST13       = 0xFFFFE000;
 	static const unsigned int MASKOFF_LOWEST12       = 0xFFFFF000;
 	static const unsigned int MASKOFF_LOWEST8        = 0xFFFFFF00;
 	static const unsigned int MASKOFF_LOWEST4        = 0xFFFFFFF0;

Modified: development/source/cpu/cHardwareCPU.cc
===================================================================
--- development/source/cpu/cHardwareCPU.cc	2009-08-13 21:51:41 UTC (rev 3366)
+++ development/source/cpu/cHardwareCPU.cc	2009-08-14 01:01:07 UTC (rev 3367)
@@ -485,6 +485,9 @@
 		// Bit Masking (higher order bit masking is possible, just add the instructions if needed)
 		tInstLibEntry<tMethod>("mask-signbit", &cHardwareCPU::Inst_MaskSignBit),
 		tInstLibEntry<tMethod>("maskoff-lower16bits", &cHardwareCPU::Inst_MaskOffLower16Bits),
+		tInstLibEntry<tMethod>("maskoff-lower15bits", &cHardwareCPU::Inst_MaskOffLower15Bits),
+		tInstLibEntry<tMethod>("maskoff-lower14bits", &cHardwareCPU::Inst_MaskOffLower14Bits),
+		tInstLibEntry<tMethod>("maskoff-lower13bits", &cHardwareCPU::Inst_MaskOffLower13Bits),
 		tInstLibEntry<tMethod>("maskoff-lower12bits", &cHardwareCPU::Inst_MaskOffLower12Bits),
 		tInstLibEntry<tMethod>("maskoff-lower8bits",  &cHardwareCPU::Inst_MaskOffLower8Bits),
 		tInstLibEntry<tMethod>("maskoff-lower4bits",  &cHardwareCPU::Inst_MaskOffLower4Bits),
@@ -6846,6 +6849,27 @@
 	return true;
 }
 
+// masks lower 15 bits in a register
+bool cHardwareCPU::Inst_MaskOffLower15Bits(cAvidaContext& ctx) {
+  const int reg = FindModifiedRegister(REG_BX);
+	GetRegister(reg) = GetRegister(reg) & MASKOFF_LOWEST15;
+	return true;
+}
+
+// masks lower 14 bits in a register
+bool cHardwareCPU::Inst_MaskOffLower14Bits(cAvidaContext& ctx) {
+  const int reg = FindModifiedRegister(REG_BX);
+	GetRegister(reg) = GetRegister(reg) & MASKOFF_LOWEST14;
+	return true;
+}
+
+// masks lower 13 bits in a register
+bool cHardwareCPU::Inst_MaskOffLower13Bits(cAvidaContext& ctx) {
+  const int reg = FindModifiedRegister(REG_BX);
+	GetRegister(reg) = GetRegister(reg) & MASKOFF_LOWEST13;
+	return true;
+}
+
 // masks lower 12 bits in a register
 bool cHardwareCPU::Inst_MaskOffLower12Bits(cAvidaContext& ctx) {
   const int reg = FindModifiedRegister(REG_BX);

Modified: development/source/cpu/cHardwareCPU.h
===================================================================
--- development/source/cpu/cHardwareCPU.h	2009-08-13 21:51:41 UTC (rev 3366)
+++ development/source/cpu/cHardwareCPU.h	2009-08-14 01:01:07 UTC (rev 3367)
@@ -712,6 +712,9 @@
 	// Bit masking instructions
 	bool Inst_MaskSignBit(cAvidaContext& ctx);
 	bool Inst_MaskOffLower16Bits(cAvidaContext& ctx);
+	bool Inst_MaskOffLower15Bits(cAvidaContext& ctx);
+	bool Inst_MaskOffLower14Bits(cAvidaContext& ctx);
+	bool Inst_MaskOffLower13Bits(cAvidaContext& ctx);
 	bool Inst_MaskOffLower12Bits(cAvidaContext& ctx);
 	bool Inst_MaskOffLower8Bits(cAvidaContext& ctx);
 	bool Inst_MaskOffLower4Bits(cAvidaContext& ctx);